An epitaxial wafer is one of the material used for a semiconductor device. The epitaxial wafer is, for example, the wafer wherein epitaxial growth of silicon is conducted on a silicon single crystal wafer, and has been widely used for many years as a wafer for manufacture of an individual semiconductor, a bipolar IC, or the like because of the outstanding characteristics. Moreover, MOS LSI have also been used as a microprocessor unit or a flash memory device since they are excellent in a soft error and latch up characteristics. An example of excellent characteristics of the epitaxial wafer is that a deterioration in reliability of DRAM or the like may be decreased since there is substantially no so-called Grown-in defect introduced at the time of manufacture of a single crystal in an epitaxial layer, and thus the need for it has been increasingly expanded.
Especially importance of an epitaxial wafer wherein epitaxial growth is conducted on a low resistivity wafer having a resistivity of 0.1 Ω·cm or less as a substrate has been increasingly raised, since it is excellent in latch up characteristics and the substrate has a gettering capacity.
On the other hand, in recent years, when metal wiring is formed on a wafer, an insulator film is formed on it, the insulator film is made plane by chemical mechanical polishing (CMP), and a metal oxide film and the 2nd metal wiring are formed on it in a manufacturing process of a semiconductor-device, it has been considered that unevenness of nano meter order in a very small area called nanotopology which exists on the polished surface of the above-mentioned wafer (which is also called nanotopography) is one of causes of loss of uniformity in a thickness of an insulator film and a poor breakdown voltage and it has come to be regarded as a problem among device makers.
The nanotopology is a shape of surface of a wafer within frequency longer than microroughness and shorter than flatness, and covers unevenness within a wavelength of around 0.1 mm to 20 mm and an amplitude of around several nm to 100 nm.
Moreover, as to planarity of the surface of the wafer, planarization has been progressed by request of lithography. With a tendency that a line width of lithography becomes finer as 0.18 μm or less due to high integration of a semiconductor device in recent years, nanotopology has been come into question. Furthermore, also in the case that STI (Shallow Trench Isolation) is filled with an insulator film and a surface is polished, it has been becoming indispensable to improve not only homogeneity of polishing of the CMP itself but also the nanotopology of a wafer itself.
Therefore, research and study of nanotopology are performed at any place not only at a device maker, but also at a material maker, a public organization and academic circles, and active argument has been developed as to a method for measuring, a quantitative definition or the like at present. However, although the nanotopology is recognized as above, it has not come to the stage where the completely unified official standard as to a measuring method and a quantitative definition of nanotopology are established.
One of the evaluation methods of the nanotopology mainly performed now is a method of evaluating difference of elevation of the unevenness on the surface of a wafer (P-V value: Peak to Valley) in the region of about 0.1 to 10 mm square or in the region of a circle with a diameter of about 0.1 to 10 mm (which is also referred to as WINDOW SIZE or the like). The P-V value is also called Nanotopography Height or the like. In evaluation of the semiconductor wafer by the nanotopography, it is especially desired that the maximum of the unevenness which exists in a plane of the wafer is small, measurement is usually performed in two or more block areas of 2 mm×2 mm square, and the maximum of the P-V value is used to evaluate the wafer. If the maximum of the P-V value is smaller, the wafer is evaluated as more excellent in quality.
Such measurement of nanotopology has been performed by WIS-CR83-SQM or NanoMapper manufactured by ADE Corporation, Surfscan-SP1-STN manufactured by KLA-Tencor Corporation, DynaSearch manufactured by New creation Corporation, NanoMetro manufactured by Kuroda Seikosha Corporation, or the like. In all of these apparatuses for measurement, measurement of unevenness is conducted optically using reflection from a surface.
Generally, such nanotopology on a surface of a wafer is considered to be determined by etching conditions, polishing conditions, or the like in a processing process of the surface of the wafer. Therefore, improvement of nanotopology characteristics is attempted mainly by studying processing conditions of the surface of the wafer, since it has been recognized to be the problem of CMP in processing of the surface of the wafer, for example, as indicated in Japanese Patent Application Laid-open (kokai) No. 2002-141311, and it is hardly attempted from the point other than processing condition of the surface of the wafer.
From now on, still severer nanotopology characteristics will be required as standard as a device size becomes still finer. Especially as to the material which bears the next generation, it is clear that it is used in the line of the latest very fine lithography, and that the wafer which has an excellent nanotopology characteristics comes to be requested inevitably.
Therefore, it is necessary that nanotopology characteristics is improved not only by the processing conditions of the surface of a wafer as before, but also from other aspects, to manufacture the wafer with very excellent nanotopology characteristics.